When it comes to designing blade embedded computers and systems for high performance embedded computing (HPEC), the VPX form factor architecture still rocks.
So far VPX has been especially suited to 1G or 10G Ethernet or PCI-express parallel computing, in systems where small size, weight, power and cost (SWaP-C) are critical, such as in many aerospace and defense applications, but also in the design of redundant architecture for critical applications.
Moving forward, VPX will still be the key to designing modular embedded computers with dedicated parallel processing architectures that deliver increased performance, withstand harsh environmental conditions, ensure reliability and continuous availability through redundancy, and enable longevity through ease of technology upgrades. Of course, such modularity depends on multiple processing, communication and I/O modules operating together in perfect harmony. Interoperability of modules through strict standardization rules is therefore essential.
If interoperability is so essential why does the latest VITA 65 OpenVPX release specify new slot profiles - some 10 years after its initial release?
At first glance this may appear a little surprising and indeed, VPX and its supporting standards VITA 46 and VITA 65 have been around quite a while. So why make such changes now? They are based on valuable lessons learned over the last 10 years of OpenVPX implementations and will help future-proof the standard to ensure it remains as one of the most successful modular computing implementations available.
VPX technology is intended for use in applications for the long term. The new VITA 65 release therefore successfully eliminates any potential confusion, ambiguity or misinterpretation in the future, by taking the opportunity to narrow down the number of profiles supporting 40G and 100G Ethernet protocols, while also improving vendor compatibility by removing user defined pins.
With the latest requirements of high-performance embedded computing systems (HPEC), the VITA 65 OpenVPX standard is ideally suited to delivering the crucial interconnect speed and flexibility, while also enabling maximum processing power in small form factor parallel computing architectures.
The higher interconnect speeds of 40G Ethernet is a perfect example of how and why VPX must keep moving with the times.
40G Ethernet means new profiles have become necessary and the VITA 65 OpenVPX standard revision 2019, under ANSI ratification process, paves the way for this and in the near future, 100G Ethernet as well. In fact, it’s already possible to evolve to 100G Ethernet for copper backplane with the use of higher performance VPX connectors, or to take advantage of optical and RF connectivity through the backplane. The new higher speed VPX connectors required are specified in the upcoming VITA 46.30 standard.
The need for speed
40G Ethernet is disrupting the ecosystem and in the world of embedded computing its arrival is creating a breakthrough in modular computing applications. The protocol is now available natively in modern CPUs and peripherals, even those designed to operate in harsh environments, and no matter if the architecture is x86 or Arm®. Further, the TCP offload engines and multi-core operation included with these implementations limit the CPU load during data movements at full throughput. This makes it very attractive to use 40G Ethernet as the main Data Plane protocol to interact between intelligent VPX modules.
Right now, however, most VPX modules or backplanes have not been designed with the goal to support 40G Ethernet as the main intra-chassis communication plane. This is creating potential pinout incompatibilities at the modules and backplane level. After all, many modules and backplanes today are PCI Express® centric, using Ethernet only as a Control Plane.
Fortunately, the release of the new VITA 65 version of the VPX specification includes a limited set of new profiles optimized for 40G Ethernet as the main primary Data Plane. These have the potential to become the new architecture baseline for the next 5 or 10 years for modular computing. The role of PCI Express® on the backplane, once the primary high-performance data movement path, is mostly assigned to be the protocol of the Expansion Plane to connect local peripheral expansion cards.
In addition to these evolutions of the next VPX VITA 65 standard, risks of interoperability between vendors are further reduced by defining all module rear I/O pin assignments: for interfaces such as Storage, Graphics, USB, UART, etc. and by removing all user-defined pins - in previous version of the standard these interfaces were implemented with user defined pins, leading to as many implementations as vendors!
Kontron is leading the way in the new VPX era
Kontron’s Intel and ARM-based VPX portfolio fully embraces the latest VPX architectures and profiles. In 3U form factor, CPU boards based on the Intel® Xeon®-D processor and featuring 40G Ethernet are available in both I/O Intensive and Compute Intensive profiles. For Ethernet switching in 3U, the VX3920 L3 switch is recommended, featuring up to 6x 40G Ethernet ports (each 40G port can also be configured as 4x 10G or 1G ports). As part of its 6U form factor range, Kontron is releasing an L3 Ethernet switch with 72 lanes allowing 100G, 40G, 10G and 1G operations. This VX6940 product adopts the new VITA 6VITA 65 profile.
In summary, the latest VPX initiatives from VITA are good news for all stakeholders concerned: manufacturers, developers and end customers. It allows us all to be on the same page when developing and implementing future HPEC solutions. It’s an ongoing challenge but one that VPX, with the benefit of its longevity and continued evolution, and the support of leading embedded computing manufacturers, is more than up to. In the final analysis, who would want a standard that stands still?
For more information about Kontron’s range of 3U and 6U VPX blade products and systems visit:
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