Supports Layers 2- through 7 functions and full deterministic processing of LTE EPC, DPI, IPTV network traffic at wire speed
Barcelona, Spain, February 15, 2011 – Kontron unveiled today the 40GbE ATCA® packet processor blade AT8242 designed with two powerful OCTEON® II cnMIPS64 multi-core processors from Cavium Networks (NASDAQ: CAVM). This represents the third generation of Kontron products based on the OCTEON family of multi-core processors and is a clear game changer for telecom equipment manufacturers seeking the most efficient, densest, open standard 40G bladed hardware. The Kontron AT8242 manages complex networking functions and provides a future-proof investment that easily scales with the expected exponential growth of converged voice, video and data traffic over IP-based networks.
The Kontron 40GbE ATCA® packet processor blade AT8242 features two OCTEON II CN6880 processors, each one integrating 32 enhanced cnMIPS64 v2 cores with up to 48GHz of 64-bit computing power in a single chip. It also combines over 85 L3-L7 application acceleration engines, virtualization features, 100Gbps of connectivity, and a new Real Time Power Optimizer™ that dynamically adjusts power depending upon the application-level processing requirement.
Customers can use the Kontron 40GbE ATCA® packet processor blade AT8242 in combination with the new Kontron 14-slot ATCA® platforms OM9141-40G and/or OM9141-10G, featuring market-leading switch management software and up to four times the I/O switching bandwidth than the previous platform generation.
The Kontron AT8242 is designed for versatility and can be used in many core and edge network applications, particularly Packet Data Network Gateways (PGW), Serving Gateways (SGW) and Mobility Management Entity (MME) network elements found in the 4G LTE Evolved Packet Core (EPC). Growth in mobile data traffic networks will require more efficient and powerful deterministic processing of applications such as packet processing, deep packet content inspection (RegEx), application-aware switching and routing, parsing, IPv6/IPv4 forwarding, compression/decompression, classification, and Quality-of-Service (QoS) at 40Gbps wire-speed.
Enhanced powerful 64bit cores from Cavium Networks
With the new and highly touted OCTEON II multi-core processors, Cavium Networks redesigned its cores from the previous generation to offer a significantly better TCP and control plane performance per core. In addition to enhanced MIPS cores, the processors also feature new dedicated hardware blocks, more memory, cache set associativity up to 37-way and a variety of new interfaces.
Each of the two OCTEON II processors – linked via Interlaken x4 interfaces – provides up to 48GHz of compute performance, and 37KB I-cache and 32KB D-cache operating at up to 1.5GHz for 3 to 4 times more performance than alternative solutions. The resulting processing and interface architecture means the CN6880 is capable of 40Gbit/s duplex line rate processing, 20Gbit/s data compression and its inbuilt DPI engines can handle 40Gbit/s of application recognition independent of the number of rules and number of flows.
DPI functions are handled by Cavium Networks’ Hyper-Finite Automata (HFA) engines, a new innovative hardware acceleration block that, in addition to the packet header information, also examines the footer, source, destination and payload information to help identify applications and protocols for more efficient network management of services. Another vital on-chip processor engine is the application acceleration manager, which processes incoming packets, queues and tags them, schedules a task to an available core and decides what will happen to the result.
The CN6880 supports 4MB of partitionable L2 cache using a HyperConnect cross-bar with more than 6 Tbps throughput. This means lower latency and improved I/O traffic performance. In addition, each cnMIPS64 core has a dedicated 37KB L1 l-cache and 32KB L1 D-cache, which provides deterministic, lower latency and improved I/O traffic performance and avoids cache ‘thrashing’.
Support for virtualization is also provided, enabling multiple instances of operating systems (OS) and other software running on top of those OSs – all on the same multi-core processor. These OSs can share all the hardware resources including I/O interfaces, memory, and packet processing offload. OCTEON II silicon also employs Cavium’s new innovative Real Time Power Optimizer™, a dynamic power management feature, which can throttle the chip's wattage up or down depending on its processing load.
Kontron AT8242 blade level design
The Kontron 40GbE ATCA® packet processor blade AT8242 complies to the following standards: PICMG® 3.0 R3.0 specification; PICMG® 3.1 R1.0 specification, and eventually PICMG® 3.1 R2.0; IPMI v2.0, and RoHS. Each OCTEON II is supported by one USB Flash drive (16GB) and 4 DDR3 DIMM sockets each supporting 32GB address range for a total of up to 256GB for both processors.
Each processor supports 2x 20Gbps and 2x 10Gbps for a total of up to 60Gbps to a Ethernet Multilayer Switch that has a bandwidth capacity of up to 320Gbps and is connected to the Fabric Interface with configurable 40/10 GbE links [2x (4x Gb / XAUI / 4x10G-KR / 40G-KR4)], and to the Base Interface with two 1GbE links.
Front panel access includes 2x RS232 - RJ45 ports – one to each OCTEON II processor – and 1x RS232 - RJ45 port to the switch management processor, and 1x 10/100/1000Base-T via RJ45 port to the switch management processor. For rear access there are two available Rear Transition Module (RTM) units, each with different connector configurations, including: RTM8242 featuring 84 Gbps total available bandwidth with 8 SFP+ (FI) and 4x GbE SFP (BI) connectors; and, the RTM8940 featuring up to 2x 40G QSFP (FI), 2x 1G SFP (BI), 4x 10G SFP+ (FI) with LRM support, and optional Telco PLL (incl. optional SyncE support).
Server management is supported by an IPMC, Dual IPMB, and Serial over LAN (IPMI v2.0) for extensive sensors monitoring and event generation on thresholds. There are two redundant Boot Block Flash BIOS and IPMI firmware with rollover.
"Kontron is a valued Cavium PACE ecosystem member and we fully support them in supplying a first-class packet processor blade on ATCA® hardware," said YJ Kim, General Manager, Multi-core Processor Group at Cavium Networks. "With the unmatched performance and integration of the OCTEON II, the Kontron AT8242 will be an essential building block to support new classes of innovative 3G/4G wireless applications that were simply not possible previously."
"The need to intelligently and cost-effectively manage the growing mobile network traffic generated across 4G LTE networks is one of many challenges faced by wireless operators around the world," said Linley Gwennap, Principal Analyst at The Linley Group. "The Cavium-Kontron design gives equipment vendors the ability to address these challenges using content inspection at up to 40Gbps line speeds."
"The marriage of open standard ATCA® hardware with the multi-core packet processor technology is a perfect match," said Simon Stanley, Analyst at Large, Heavy Reading. "A Kontron designed ATCA® blade with the OCTEON II architecture will be an appealing and scalable solution that can deliver the performance required for the complex network functions that handle intelligent routing, data center virtualization, storage, 4G/LTE wireless, HD video over the Internet, and multimedia rich Web 2.0 applications."
"Kontron customers are in an extremely competitive race to be first to market with innovative solutions that feature significantly more efficient and intelligent multi-core processing, such as that supplied by the OCTEON II processors from Cavium Networks," said Dirk Finstel, CTO of Kontron. "We are exceptionally pleased to add the 40G ATCA® packet processor blade Kontron AT8242 to our new line of application-ready 40G ATCA® platforms."
Early samples of the Kontron 40GbE ATCA® packet processor blade AT8242 will be available for evaluation in Q2, 2011.
Kontron is available to further discuss details of the Kontron AT8242 during Mobile World Congress, at Booth 2A28 in Hall 2.0, on February 14-17, 2011.
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